The present invention relates to a printhead, head cartridge having said printhead, printing apparatus using said printhead and printhead element substrate, and more particularly, to a printhead having a plurality of painting elements and a drive circuit for driving the printing elements aligned in a predetermined direction on an element board, a head cartridge having such a printhead, a printing apparatus using such a printhead, and a printhead substrate.
In a printing apparatus used as an information output device for a word processor, personal computer or facsimile network and the like to print desired text or image information on paper, film or some other sheet-like printing medium, a serial printing method is in general and widespread use due to its inexpensiveness and ability to be made compact.
In order to facilitate an understanding of the present invention, a description will now be given of the composition of the printhead used in such a printing apparatus, using the example of a printhead that follows the ink jet method that uses thermal energy to print. For the printing element, this type of ink jet printhead provides heating elements, or heaters, at that portion of the head that is continuous with the nozzles that actually discharge the drops of ink. An electric current is then applied to the heaters, causing the heaters to boil the ink and forcing ink drops through the nozzles by the expansion of the bubbles formed in the ink when boiled. This type of printhead easily accommodates compact, high-density arrangements of nozzles and heaters, by means of which high-definition printing images can be obtained.
The heater board of the printhead of a printer that uses heaters for the heating element is supplied with power from the printer main unit by two power supply systems: a 10-30V, high-voltage power supply for driving the heaters, and a 5V power supply for the logic circuits that control the driving of the heaters.
The heater power source VH, together with the signal supplied to the logic circuit, is connected to the heater board from the printer via flexible substrate wiring that connects the main unit and the carriage, a contact pad (connection terminal) on the carriage that connects to the head, and tab wiring inside the printhead. The wiring and contact pad have resistance, inductance and capacitance impedance components, so fluctuations in current as the heater turns ON and OFF causes large, precipitous fluctuations in the heater power source VH voltage. This voltage fluctuation is superimposed on the logic signal via the flexible substrate wiring.
In order to prevent faulty operation of the heater board logic circuit due to the effects of noise mixed in with the logic signal, the input part of the logic circuit is provided with a Schmitt trigger that gives the threshold voltage for discriminating between high-level and low-level logic signals a hysteresis property as between the rising waveform and the falling waveform of the input signal.
FIG. 1 is a block diagram showing the circuit structure of a heater board of a typical ink jet printhead. From the printer main unit, a heater drive signal HE, latch signal LT, clock signal CLK and data signal DATA, respectively, are input from respective contact pads 510. The data signal DATA is synchronized with the clock signal CLK and input into a shift register, and is held in a latch 505 with the input of the latch signal LT. The logical product of the output from the latch 505 and the heater drive signal (HE) is ANDED by an AND circuit 504, and depending on that output the drive element 502 is turned ON via a buffer 503 and a heater 501 is activated (that is, driven).
In an ink jet printhead heater board circuit, a Schmitt trigger 508 is provided between each of the signal contact pads 510 and buffers 507. The Schmitt trigger used in this type of circuit may be that which is described in Japanese Laid-Open Patent Application No. 08-039809.
A description will now be given of the operation of a Schmitt trigger with reference to FIGS. 2A and 2B, in a case in which the supply voltage Vdd is 5 V and the signal waveform rising and falling threshold voltages are 3.5 V and 1.5 V, respectively.
FIGS. 2A and 2B are diagrams illustrating a Schmitt trigger and the operating characteristics thereof.
In FIG. 2A, reference numeral 100 denotes a MOS inverter with a threshold of 3.5 V (that is, 70% of the supply voltage Vdd), reference numeral 101 denotes a MOS inverter with a threshold of 1.5 V (that is, 30% of the supply voltage Vdd) and reference numeral 102 denotes a MOS inverter with a threshold of 2.5 V (that is, 50% of the supply voltage Vdd). Reference numerals 103 and 104 are NAND circuits, respectively.
The input-output characteristics of this circuit are as shown in FIG. 2B, in which, when a signal indicated by dotted line 10 is input, a flip-flop composed of NAND circuits 103 and 104 is initially reset and the output signal 111 is LOW. Then, when the input signal 110 exceeds 0.7 Vdd, the inverter 100 output becomes LOW, the NAND circuit 103 output becomes HIGH and the output signal 111 is HIGH. Next, when the input signal 110 voltage drops and the electric potential falls below 0.3 Vdd, the inverter 101 output inverts and switches to HIGH and the NAND circuit 104 output inverts to LOW, making the output signal 111 LOW.
Next, a description will be given of the composition of a signal that changes the threshold values of the MOS inverters 100 and 101, with reference to FIG. 3.
FIG. 3 shows the layout of a MOS inverter. As shown in the diagram, L and W show the length and width, respectively, of the MOS-construction FET gate. Additionally, reference numeral 120 denotes an input signal line input from the pad and reference numeral 121 denotes the output signal line.
In a typical MOS inverter, the ON resistance of the PMOS and NMOS is practically identical, and is designed so that the threshold is a central 0.5 Vdd. By changing the length L and width W of the gate shown in FIG. 3, the channel resistance value can be increased or decreased. Accordingly, with respect to the inverter 100 of FIG. 2A, the length and width of the gate are set so that the ON resistance (NMOS) is greater than the ON resistance (PMOS), and with respect to the inverter 101, the length and width of the gate are set so that the ON resistance (NMOS) is less than the ON resistance (PMOS). As a result, as shown by the hysteresis characteristic of FIG. 2B, inverter circuits of different threshold values can be formed on the same heater board by any common logic circuit production process.
Next, a description will be given of the Schmitt trigger having hysteresis characteristics and formed by using two inverters of different thresholds as described above, with reference once again to FIG. 2A.
Reference numeral 106 in FIG. 2A denotes an input pad and P1-P6 denote points for indicating a voltage or a logic level. When the electric potential of the signal input from the input pad 106 changes from 0 V to 1.5 V, because the inverter 101 input signal threshold is 1.5 V the electric potential at point P3 changes from HIGH to LOW and the electric potential at point P4 also changes from LOW to HIGH.
Further, when the electric potential of the signal input from the input pad 106 changes from 1.5 V to 3.5 V, because the inverter 100 input threshold is 3.5 V the inverter 100 output inverts and the electric potential at point P2 becomes LOW. As a result, the NAND circuit output (PS) electric potential level inverts to HIGH. Thus it is clear that the output P5 becomes HIGH only after the input signal electric potential is 3.5 V. In this state, the output signal level is maintained even if the electric potential at the input pad rises further.
If the electric potential of the signal input from the input pad 106 falls from 5 V to 0 V, then the inverter 100 with an input threshold of 3.5 V inverts before the inverter 101 when the electric potential at point P1 is 3.5 V. In this case, however, because the electric potential at point P6 is LOW there is no impact from the output P5. Then, when the electric potential at the input pad falls to 1.5 V, the inverter 101 inverts, the output (point P3) of that inverter 101 becomes HIGH, the point P4 electric potential becomes LOW and the output P5 changes to LOW.
As described above, by giving the printhead heater board input signal a hysteresis characteristic, a hysteresis characteristic with a higher noise margin can be obtained in which the input signal level can rise to 3.5 V without the output inverting when the input signal is LOW (0 V) and the input signal can fall to 1.5 V or less without the output inverting when the input signal is HIGH (3.5 V or more).
However, a parallel interface is usually used for the conventional printer interface. In that case, a voltage of 5 V is used as the power source for the logic circuitry of the printer main unit, and that 5 volts is also used to supply power to the logic circuitry of the ink jet printhead substrate inside the head. Additionally, a portion of the integrated circuits of the printer""s internal circuitry also requires a power supply of 5 V, which is one reason the logic voltage of the ink jet printhead substrate has been designed to be 5 V.
However, recently, improvements in the miniaturization technologies that lay down IC design rules and the adoption of new interfaces have made the use of a 5 V printer main unit power supply increasingly impractical in terms of cost and size. It is for this reason that there have been moves afoot to adopt 3.3 V as the mainstream printer main unit logic supply voltage. Nevertheless, it has been established that reducing the head substrate logic supply voltage from the proven 5 V to 3.3 V creates a number of problems, which are described below with reference to FIG. 4.
FIG. 4 is an example of the structure of the substrate (hereinafter also referred to as an xe2x80x9celement boardxe2x80x9d) used for a typical ink jet printhead. In the diagram, reference numeral 1003 is a pad for receiving an external signal. As shown in the diagram, the pad 1003 includes a Vdd terminal 1006 for receiving a logic supply voltage, a VH terminal 1008 for receiving a heater drive supply voltage, a GNDH terminal 1005 that is grounded, and a VSS terminal 1007. Additionally, as shown in the diagram, a shift register logic circuit 1002 for receiving image data serially and outputting such data in parallel, a driver 1001 for driving a heater and a heater 1004 are arranged on a single silicon substrate.
A case involving formation of a 620-bit heater is depicted in further detail in FIG. 5.
FIG. 5 is a block diagram of an ink jet printhead substrate.
As shown in the diagram, the 620-bit heater is designed so as to drive a maximum of 40 bits simultaneously, repeated 16 times so as to drive all of the 620-bit heaters (in one cycle).
FIG. 6 is a drive timing chart for an ink jet printhead. A description will now be given with reference to FIG. 6 of the speed required to send image data when driving all 620 bits, where the drive frequency required to carry out constant high-speed printing is 15 kHz (existing equipment will suffice for this purpose).
A drive frequency of 15 kHz results in a period (cycle) of 66.67 xcexcS, within which 40 bits of image data must be sent in 16 blocks, which means that the image data transmission speed must be at least 12 MHz or more. This transmission speed is not large when considered within the context of the capabilities of an ordinary CPU, but in the case of an ink jet printhead, the fact that the working carriage and the main unit are connected by a long, flexible element board and that printers themselves have become smaller requires the carriage to be made more compact as well. As a result, the 12 MHz figure is by no means a small one.
A description of the reduction in transmission capacity when the logic supply voltage is reduced from 5 V to 3.3 V will now be given with reference to FIGS. 7A and 7B.
FIGS. 7A and 7B are diagrams showing logic supply voltages versus image data transmission-capable maximum clock frequencies and element board temperature versus image data transmission-capable maximum clock frequencies, respectively.
As shown in the diagrams, as the logic signal supply voltage drops the clock frequency declines, because the drive performance of the MOS transistor used for the shift register part and the clock and other input circuitry for performing image data transmission declines simultaneously with the decline in the logic supply voltage used as the gate voltage of the CMOS. As can be understood from the diagrams, the drop in gate voltage causes the drive performance (that is, the drain current Id) to decline.
Moreover, driving the heaters on the element board of the ink jet printhead imposes thermal requirements on top of speed requirements. These added thermal requirements are specific to ink jet printhead substrates. Thus, as shown in FIG. 7B, the performance of the ink jet printhead declines as the temperature of the element board increases together with the decline in capacity attendant upon use of a 3.3 V power supply.
From the foregoing, it is clear that the performance must be enhanced with the 3.3 V arrangement, in a way that was not an issue for the conventional 5 V, 12 MHz clock frequency.
In order to facilitate an understanding of the present invention, a further description will now be given of the cause of the above-described decline in image data transmission capacity with a Schmitt trigger as the voltage is lowered.
As the power supply voltage is lowered, the gate voltage that drives the MOS transistor that composes the logic circuit also declines.
FIG. 8 is a graph showing the relation between drain current (Id) and drain-source voltage (Vds) in a MOS transistor when the gate voltage (Vgs) is varied.
As can be seen from FIG. 8, when the gate voltage (Vgs) drops from 5 V to 3.3 V, the transistor current drive capacity declines by over half.
FIG. 9 is a diagram showing the gate capacity load added to the inverter output when a CMOS inverter is used to drive a MOS transistor gate.
If a MOS transistor gate is driven with a CMOS inverter as shown in FIG. 9, then in effect the gate capacity load is added to the inverter output. If the MOS ON resistance is RMOS and the equivalent load capacity is Cgate, then the delay time constant from the time the inverter input changes to the time the output inverts is Cgate X RMOS. Lowering the supply voltage without changing the load more than doubles the RMOS, and thus also more than doubles the delay time constant.
In the Schmitt trigger depicted in FIG. 2A, from input of the Schmitt trigger to output, the number of steps of the operating inverter differs between the rising waveform and the falling waveform, and it is for this reason that the delay time of the inverters increases as the voltage is lowered, which in turn causes the length of the delay of the Schmitt trigger with respect to the input waveform rising edge and falling edge to differ from the conventional delay by as much as a factor of two or more.
When the supply voltage is 5 V the ON resistances are sufficiently small that the difference between the rising delay and the falling delay is minor and can be ignored. However, reducing the supply voltage also reduces the drive gate voltage in an MOS transistor, increasing the ON resistance and, as a result, increasing the difference in the extent of the rising delay and the falling delay to the point where the difference can no longer be ignored.
A difference in the delay between the rising edge and the falling edge of an input waveform in a Schmitt trigger leads to the following problems.
FIG. 10 shows a Schmitt trigger signal waveform in which a delay is imposed at the rising and falling edges of an input signal.
As shown in the diagram, the input signal waveform is indicated by a solid line and the shift register waveform is indicated by a dashed line. As is clear from the solid line indicating the input signal waveform, the set-up time and the hold time that comprise the margin of DATA change with respect to changes in the CLK is the same for the input waveform. However, as shown by the dashed line indicating the shift register waveform, a waveform that has passed through a Schmitt trigger has a reduced set-up time and hold time as compared to those of the input waveform.
When the set-up time and the hold time margins decrease at the shift register input as described above, reliable data acquisition becomes problematic, which can cause malfunctions. Additionally, it becomes difficult to increase the clock frequency and carry out high-speed data acquisition.
Additionally, the heater board is a part of the printhead which is an expendable component, so it is used in common in a wide variety of printers and existing layouts. As a result, circuit configurations have been studied extensively in terms of reducing costs and streamlining manufacturing, that is, standardizing the product. Accordingly, adding a new component as a result of lowering the supply voltage imposes not only a requirement to not complicate the manufacturing process but also a requirement to study such an addition carefully in order to not upset the overall balance.
Moreover, recent demands for and improvements in printer printing speed and printing resolution continue to grow apace, with the result that consumers still require improved printing speed even with a lowered supply voltage.
Accordingly, the present invention was developed in order to solve the problems of the conventional art described above, and has as its object to provide a printhead that, when operating with a lowered supply voltage, can reduce the difference in delay between the rising edge and the falling edge of an input waveform between the input and output of a Schmitt trigger and can accommodate high-speed data transmission, while imposing no additional manufacturing costs.
Another object of the present invention is to provide a head cartridge adapted to use the above-described printhead.
Another and further object of the present invention is to provide a printing apparatus that uses the above-described printhead.
Still another and further object of the present invention is to provide a printhead element substrate that reduces the difference in delay at the rising edge and the falling edge of a given input waveform at the Schmitt trigger between input and output without increasing manufacturing costs when the supply voltage is lowered, and can accommodate high-speed data transmission.
The above-described objects of the present invention are achieved by a printhead in which a plurality of printing elements and a drive circuit for driving the printing elements are provided on a single element substrate, the printhead comprising a Schmitt trigger having hysteresis characteristics that cause a threshold value for a rising edge of a waveform of a logic signal input into the drive circuit and a threshold value of a falling edge of a waveform of a logic signal input into the drive circuit to be different, and delay adjustment means for adjusting a length of a delay at the rising edge and a length of a delay at the falling edge occurring when the threshold values of the rising edge and the falling edge of the input signal waveform differ.
Additionally, the above-described objects of the present invention are achieved by a head cartridge comprising the printhead as described above, and an ink tank adapted to hold ink to be supplied to the printhead.
Additionally, the above-described objects of the present invention are achieved by a printing apparatus comprising the printhead described above, wherein the printing apparatus performs printing using the printhead.
Additionally, the above-described objects of the present invention are achieved by a printhead element substrate, in which a plurality of printing elements and a drive circuit for driving the printing elements are provided on a single element substrate, the printhead element substrate comprising a Schmitt trigger having hysteresis characteristics that cause a threshold value for a rising edge of a waveform of a logic signal input into the drive circuit and a threshold value of a falling edge of a waveform of a logic signal input into the drive circuit to be different, and delay adjustment means for matching a length of a delay at the rising edge and a length of a delay at the falling edge occurring inside the Schmitt trigger at the rising edge and the logic signal.
In other words, in the present invention, the delays at the rising and falling edges of the input waveform of the logic signals input to the drive circuit are adjusted at the Schmitt trigger.
By so doing, the two delays can be made substantially identical, so the speed of data transmission to the printhead can be increased even as the supply voltage is lowered.
It should be noted that it is preferable that the data be read at the rising and falling edges of the logic signals.
In such cases, the logic signals consist of at least a clock signal and a data signal.
Optimally, the delay adjustment means is provided inside the Schmitt trigger.
It is preferable that a Schmitt trigger be provided for each logic signal to be input to the drive circuit.
In such a case, the Schmitt trigger may be configured so that the number of elements along the path traversed by the rising edge of the logic signal and the number of elements provided along the path traversed by the falling edge of the logic signal is different, with the delay adjustment means being provided along the path of fewer elements.
Specifically, the Schmitt trigger may be configured so that the number of inverters included in the path traversed by the falling edge of the logic signal is greater than the number of inverters included in the path traversed by the rising edge of the logic signal, and the delay adjustment means is provided along the path traversed by the rising edge of the logic signal.
Alternatively, the Schmitt trigger may be configured so that the number of inverters included in the path traversed by the falling edge of the logic signal is greater than the number of inverters included in the path traversed by the rising edge of the logic signal, and the length of the delay at a rising edge of the waveform logic signal and the length of the delay at the falling edge of the waveform logic signal is adjusted by adjusting an ON resistance of at least one inverter included in one path or the other.
Preferably, the length of the delay at the rising edge and the length of the delay at the falling edge are adjusted to be substantially identical.
Other objects, features and advantages of the present invention besides those discussed above shall be apparent to those skilled in the art from the description of a preferred embodiment of the invention which follows. In the description, reference is made to accompanying drawings, which form a part thereof, and which illustrate an example of the invention. Such example, however, is not exhaustive of the various embodiments of the invention, and therefore reference is made to the claims that follow the description for determining the scope of the invention.